Short for the SPI Memory Emulator.
It is implemented on a Xilinx Spartan 3 FPGA board in Verilog. A 1MB SRAM buffer is concurrently accessible by the PC over a 3 MBit serial port, and by the DS over an SPI EEPROM emulator. This buffer can store normal save files, plus it can be used as a fast communication channel for memory dumps, commands to execute, etc.
This shared memory buffer can also be used to send simple RPC-like commands to the DSi, implementing a very simple debug monitor for poking at registers in real-time.
Source code is under a BSD-style license, available from a public Subversion repository.